PCI
This
is old 32 and 64 bit PCI.
PCI-X
The PCI-X uses all the same
connectors and stuff as "conventional" PCI. The transfer speed added
to the end, as in "PCI-X 66" (which supports a 66MHZ clock rate) or
"PCI-X 133" (which supports a 133Mhz clock rate). In a PCI-X system,
the system runs at the speed of the slowest device. Due to backward
compatibility requirements, all PCI-X devices must be able to run at lower
speeds to work in older systems or PCI-X systems with a slower device or PCI
device. At 133 MHz, the PCI-X bus can accommodate only one PCI-X device and, at
100 MHz, can accommodate two PCI-X devices. At 66 MHz, it can accommodate four
or more devices. Note that designers introduced the 100-MHz version to give
designers the opportunity to trade off between number of slots and bus
speed/bandwidth. You can use a PCI-X bridge at higher speed to increase the
number of available slots in the system. PCI-X also supports 32- or 64-bit-wide
data buses. Because the data is transfered in parallel, either 32 or 64 bits at
a time, this means that PCI-X 64-bit/100MHz = 800MB/s, PCI-X 64-bit/133MHz =
1GB/s
|
Bus and Frequency
|
Peak 32-Bit Transfer
Rate
|
Peak 64-Bit Transfer
Rate
|
|
33-MHz PCI
|
133 MB/sec
|
266 MB/sec
|
|
66-MHz PCI
|
266 MB/sec
|
532 MB/sec
|
|
100-MHz PCI-X
|
N/A
|
800 MB/sec
|
|
133-MHz PCI-X
|
N/A
|
1 GB/sec
|
|
AGP8X
|
2.1 GB/sec
|
N/A
|
PCI Express
This is an entirely new bus
architecture, previously known by the name "3GIO." It performs serial data transfers. The basic
"x1" link has a peak raw bandwidth of 2.5 Gbps. Data is transferred
in packets, and effectively routed via a switch. Transfers are bi-directional, so data can
flow to and from a device simultaneously.
Since data is switched, more than 1 device can be transferring at the
same time. So because PCI-E is a point-to-point serial connection, total bus
bandwidth is no longer an issue. PCIe is usually specified as x1, x4, x8, and
x16c. This specifies the number of “lanes” that the slot offers. A lane is a
bi-directional serial channel capable of around 250MB/s in each direction
(sending and receiving). So an x16 slot should be 4GB/s in each
direction.(Total 8GB/s)
PCI Express uses 8b/10b encoding,
which encodes 8-bit data bytes into 10-bit transmission characters. This is
improves the physical signal so that bit synchronization is easier, receivers
and transmitters is simplified, error detection is improved, and control
characters can be distinguished from data characters.
Basic,
encoded, x1 PCI Express lane is 5 Gbps. But more accurate bandwidth is the
unencoded, which is 80 percent of 5 Gbps or 4 Gbps.
|
PCI Express
Implementation
|
Encoded Data Rate
|
Unencoded Data Rate
|
|
x1
|
5 Gbps
|
4 Gbps (500 MB/sec)
|
|
x4
|
20 Gbps
|
16 Gbps (2 GB/sec)
|
|
x8
|
40 Gbps
|
32 Gbps (4 GB/sec)
|
|
x16
|
80 Gbps
|
64 Gbps (8 GB/sec)
|
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